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MK2069-01
VCXO-BASED LINE CARD CLOCK SYNCHRONIZER
VCXO AND SYNTHESIZER
IDT VCXO-BASED LINE CARD CLOCK SYNCHRONIZER
3
MK2069-01
REV K 051310
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
ST0
Input
Scaling Divider bit 0 input, Translator PLL (internal pull-up).
2
ST1
Input
Scaling Divider bit 1 input, Translator PLL (internal pull-up).
3
RT0
Input
Reference Divider bit 0 input, Translator PLL (internal pull-up).
4
RT1
Input
Reference Divider bit 1 input, Translator PLL (internal pull-up).
5
FT0
Input
Feedback Divider bit 0 input, Translator PLL (internal pull-up).
6
FT1
Input
Feedback Divider bit 1 input, Translator PLL (internal pull-up).
7
FT2
Input
Feedback Divider bit 2 input, Translator PLL (internal pull-up).
8
FT3
Input
Feedback Divider bit 3 input, Translator PLL (internal pull-up).
9
FT4
Input
Feedback Divider bit 4 input, Translator PLL (internal pull-up).
10
FT5
Input
Feedback Divider bit 5 input, Translator PLL (internal pull-up).
11
RV0
Input
Reference Divider bit 0 input, VCXO PLL (internal pull-up).
12
VDDT
Power
Power Supply connection for translator PLL.
13
GNDT
Ground
Ground connection for translator PLL.
14
X1
-
Crystal oscillator input. Connect this pin to the external reference crystal.
15
VDDV
Power
Power Supply connection for VCXO PLL.
16
X2
-
Crystal oscillator output. Connect this pin to the external reference crystal.
17
GNDV
Ground
Ground connection for VCXO PLL.
18
LFR
-
Loop filter connection, reference node. Refer to loop filter circuit on page 6.
19
LF
-
Loop filter connection, active node. Refer to loop filter circuit on page 6.
20
ISET
-
Charge pump current setting input. Refer to loop filter circuit on page 6.
21
FV0
Input
Feedback Divider bit 0 input, VCXO PLL (internal pull-up).
22
FV1
Input
Feedback Divider bit 1 input, VCXO PLL (internal pull-up).
23
FV2
Input
Feedback Divider bit 2 input, VCXO PLL (internal pull-up).
24
FV3
Input
Feedback Divider bit 3 input, VCXO PLL (internal pull-up).
25
FV4
Input
Feedback Divider bit 4 input, VCXO PLL (internal pull-up).
26
FV5
Input
Feedback Divider bit 5 input, VCXO PLL (internal pull-up).
27
FV6
Input
Feedback Divider bit 6 input, VCXO PLL (internal pull-up).
28
FV7
Input
Feedback Divider bit 7 input, VCXO PLL (internal pull-up).
29
FV8
Input
Feedback Divider bit 8 input, VCXO PLL (internal pull-up).
30
FV9
Input
Feedback Divider bit 9 input, VCXO PLL (internal pull-up).
31
FV10
Input
Feedback Divider bit 10 input, VCXO PLL (internal pull-up).
32
FV11
Input
Feedback Divider bit 11 input, VCXO PLL (internal pull-up).
33
MX1
Input
Input MUX selection bit 1 (internal pull-up).
34
ICLK2
Input
Reference clock input 2.
35
ICLK0
Input
Reference clock input 0. 5V tolerant input.
36
CLR
Input
Clear input, clears VCXO PLL dividers when low (internal pull-up).
37
LDC
-
Lock detector threshold setting circuit connection. Refer to circuit on page 10.
38
GND
Ground
Digital ground connection.
39
LDR
-
Lock detector threshold setting circuit connection. Refer to circuit on page 10.
40
RCLK
Output
VCXO PLL phase detector Reference Clock output.
41
GNDP
Ground
Ground connection for output drivers (VCLK, TCLK, RCLK, LD, LDR).
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